//FileName   : clkgen
//Author     : -
//Description: clkgen
//ModifyDate : 2019-5-4
//Company    : -
//Copy right : -


module clkgen (
    output reg          clk,
    output reg          rst_n
);



//-------- verbose --------
    initial begin
        clk = 0; rst_n = 1;
        #5 clk = 1;rst_n = 0;
        #20 rst_n = 1; clk = 0;
        forever
          #5 clk = ~clk;
   end


endmodule
